This is a software development project requested by Herb Johnson. He wanted a complete CPM-80 system developed around a simple floppy disk controller. He wants it to run on a 2 MHz 8080 processor with no tricky code or DMA.
Here are pictures of the board:
The Versafloppy II floppy disk controller will be used. It is a solid board with with no frills. Documentation is available for it here. It is based on the Western Digital FD-1795B02 FDC chip. The datasheet is here.
The processor will be an 8080 runnning a 2 MHz. All code will be in 8080 mnemonics.
The VersaFloppy II depends on the now nonexistant Theta 1 clock. The board must be modified to develop this signal by inverting Theta 2 with one section of a 74LS04. This modification is shown below:
The modification consists of the following changes: 1) Pulling U9 out, bending pin 5 out and replacing U9. 2) Bending pins 1, 3-6, 9-13 of a 74LS04 straight out to the side. 3) Connect pin 13 to 3 to 11 to 5 to 9 (unused inputs) together with a wire. 4) Mount the 74LS04 over U34 by soldering pin 2 to U34 pin 3 (requires bending pin back), pin 7 to 7 and 14 to 14. 5) Connect a 4.7 K resistor between any of the unused inputs to pin 14. 6) Connect pin 10 of the 74LS04 to the thru hole between U26 and U27 as shown on the diagram above.
With the modification completed, I placed the board into the S-100 machine. I was able to read and write to ports 63H-67H from the monitor or DDT. This means the board is operating and it was time to connect some drives. I connected a pair of 5.25" 360 KB drives to the disk controller. I powered the drives with a small 5/+12/-12 VDC power supply.
I was able to home either drive and seek other sectors on either drive. The 179X will NOT read or write without a RDY signal from the drive. 5.25" drives don't provide the RDY signal and the 34-pin connector does not tie RDY to the controller. The 5"/8" switch (74LS157) shows it ties RDY to ground for 5" drives. This is an error on the diagrams, the revision K being the latest I can find. All the boards I have are revision P. This line is tied high. Took a bit to get the bits in register 63H correct to get RDY right. The head load bit, which is incorporated in some of the 179X commands actually loads the heads and starts the motors. The board has delay one-shots for each size drive.
I am using the two CCP and one BDOS image used in the V81/V82 code. I will have to develop a completely different BIOS in the V83 code to support FDDs on the SDSystems VF II. The test system will still boot the V82 8-inch disks.
In the 35 years since the floppy disk was introduced defacto standards have developed. Today, the MSDOS standard for a 360K 5.25-inch disk is DSDD, 9 each 512 byte sectors on each side. Data is written on alternate heads. I will use this standard for my 5.25-inch disk format.
A boot disk normally contains a BOOT sector (logical sector 0) followed by the DATA. In the CPM-80 world, we don't need the BOOT sector and put the BIOS image on the disk on the rest of track 0, and the CCP + BDOS on track 1. CPM-80 DIRECTORY and DATA are on the tracks 2-39. To boot a CPM-80 system, the BIOS is loaded off track 0 at its operational address and a jump is done to the cold boot location. The BIOS will then load CCP + BDOS and start the operating system.
One thing to resolove is determining the floppy disk format when a disk is loaded into the machine. I have resolved this by using an IDENTITY Sector which contains the DPB defining the disk structure and some other elements to simplify BIOS. This has worked well in the 8-inch world for me over several CPM-80/86 systems. I will use the BOOT sector on the 5.25-inch floppy disk for this purpose.
Herb Johnson and I discussed the question of a BOOT sector. We decided that a BOOT sector was desirable. So I combined the BOOT and ID sectors.
The 5.25-inch floppy disk will be layed out as follows:
Track 0, Head 0, Sector 1 - BOOT/ID Sector
Track 0, Head 0, Sector 2-9 - BIOS
Track 1, Head 0, Sector 1-2 - CCP
Track 1, Head 0, Sector 3-9 - BDOS
Track 2, Head 0, Sector 1-... - DATA
I have built a "probe" to watch the signals on the DC-37 cable used on my standard 5.25/3.5-inch drives with my logic analyzer. This is covered here.
Debugging with the "probe" demonstrated my lack of understanding of some of the signal lines between the VF II and the FDDs. I have the correct definitions for the signals normal or inverted states.
I have also changed the CPU clock speed to 5 MHz during initial development phase. This increases the probability I can actually read a disk sector with a simple loop of 8080 code!
I connected the host system back up with the VF II board and connected the VF II to a pair of 360KB 5.25 inch FDDs. With the Logic Analyzer on the disk cable, I can see the functioning of all the signal lines. I have verified that the signals are being asserted in the correct sense from the VF II. I have a pair of 360KB MSDOS formatted disks in the FDDs.
I have taken the Floppy Disk Exerciser (FDE) program from the iSBC 80/10 and generalized it - moved all the disk primitives to one place in the file. I will modify it to operate the JadeDD FDC then get it to work with the VF II.
Last revised 7 December 2014.